Lattice Semiconductor
Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.
- (503) 268-8000
- (503) 268-8169
- 5555 NE Moore Ct,
Hillsboro,, OR 97124
United States
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Low-power, High-performance FPGA
iCE40 LP/HX
*Available in three series with LUTs ranging from 384 to 7680: Low power (LP) and high performance (HX)*Integrated hard I2C and SPI cores that enable flexible device configuration through SPI*Match your preferred display to your application processor with interfaces such as RGB, 7:1 LVDS and MIPI DPI/DBI*Multi-source your image sensors by implementing flexible bridges supporting common interfaces such as HiSPi, subLVDS, LVDS and Parallel LVCMOS*Up to 128 kbits sysMEM™ Embedded Block RAM*Industry’s broadest range of 0.35 mm - 0.40 mm pitch BGAs fit in space-constrained applications
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Enabling Low Power, High Reliability, And High Performance Design
Lattice Nexus Platform
The Lattice Nexus FPGA platform combines Lattice’s long-standing low power FPGA expertise with leading 28nm FD-SOI semiconductor manufacturing technology. With this platform, Lattice enables the rapid development of multiple device families that deliver low power, high performance, high reliability and small form factor.
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Manage Power, Thermal & Control Planes In Real Time
Platform Manager 2 & L-ASC10
*Full fault coverage – monitor all rails and temperature nodes*Manage from 10 to 80 supplies using just the required number of L-ASC10 hardware management expanders*Minimize fault propagation by enabling individual hardware management sub-blocks (power, thermal & control path) to respond to faults in other blocks within nano-seconds*Save CPLD I/O pins by eliminating the need to monitor power-good signals of DC-DC converters*Reliable power & thermal fault detection in hardware, as opposed to software routines
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FPGA Design, Meet Easy.
Lattice Diamond Software
Easy Design Exploration – Finding the best solutions often requires evaluating multiple solutions. Lattice Diamond allows for easy design exploration.
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Bridging And I/O Expansion Versatility. Rapid Hardware Acceleration For Improved Signal Control.
MachXO2
*Up to 256 kbits of user Flash memory and up to 240 kbits sysMEM™ embedded block RAM*Up to 334 hot-socketable IOs that avoid excess leakage*Programmable through JTAG, SPI, I2C or Wishbone*TransFR feature allows in-field design update without interrupting equipment operation*Programmable sysIO™ buffer supports LVCMOS, LVTTL, PCI, LVDS, BLVDS, MLVDS, RSDS, LVPECL, SSTL, HSTL and more
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Low Power MIPI Bridging Solution With Integrated Flash
CrossLinkPlus
*Instant-on (< 10 ms) configuration with integrated flash memory*Integrated flash enables flexible reprogramming in the field*Two 4-lane MIPI D-PHY transceivers at 6 Gbps per port*11 programmable, source synchronous I/O pairs for camera and display interfacing*Available in small 3.5 mm x 3.5 mm BGA package with 0.4 mm pitch*Comprehensive library of IP and reference designs, compatible with CrossLink
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Get Flexible, Get FlexiFLASH
LatticeXP2
*Up to 885 Kbits sysMEM™ embedded block RAM and up to 83 Kbits distributed RAM*sysCLOCK™ PLLs up to four analog PLLs per device that enable clock multiply, divide and phase shifting*Three to eight sysDSP blocks for high performance multiply and accumulate.*Pre-engineered source synchronous IOs for DDR/DDR2 up to 200 MHz and 7:1 LVDS interface support up to 600 Mbps*Available in csBGA, TQFP, PQFP and BGA packaging
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Efficiency And Innovation, Squeezed Into One Tiny, Affordable Package
LatticeECP3
*Up to 16 channels at 3.125 Gbps*800 MBps DDR3, 1Gbps LVDS*Up to 586 programmable sysIO buffers with support for PCI Express, Ethernet (GbE, XAUI, & SGMII), HDMI, SMPTE, Serial Rapid I/O, CPRI and JESD204A/B and more*Up to 150 k LUTs and 6.8 Mbits of SRAM*Wide array of packages as small as 10.0 mm x 10.0 mm with power consumption below 0.5 W
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Lattice SensAI Studio
Graphical interface based tool to help users built accelerated machine learning applications quickly. Select from a range of models pretrained to cover popular use cases, bring in your own data for additional training, validation the quality of training using TensorBoard, compile for Lattice’s FPGAs*Model Zoo with variety of models based on multiple architecture*Easy to use labeling, training, and compilation GUI*Docker container provided for installation on your own machine or server*Free license
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Hardware Security For Programmable System Control
Mach-NX
*Up to 8.4K LC of user logic, 2669 kbits of user flash memory and dual boot flash feature*Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages*Secure enclave supports 384-bit cryptography, including SHA, HMAC, and ECC*Configuration of PFR and security functions through Lattice Propel simplifies developer experience*Highly reliable. Low power and 3X better SER performance to comparable CMOS technologies
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Low Power FPGA Featuring Hardened MIPI D-PHY, LVDS, SLVS, SubLVDS, & Open LDI Bridging
CrossLink
*Two 4-lane MIPI D-PHY transceivers at 6 Gbps per PHY*15 programmable source synchronous I/O pairs for camera and display interfacing*Available in amazingly small 2.46 mm x 2.46 mm WLCSP packages and BGA packages with 0.4 mm, 0.5 mm and 0.65 mm pitch
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Futureproof Your Control PLD And Bridging Designs
MachXO3
*Up to 9400 LUTs with up to 384 I/O pins*Instant-on 1 ms boot-up with background upgrade, Hitless I/O reconfigure and dual-boot error recovery*Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices*MachXO3LF includes programmable Flash and User Flash Memory (UFM)*Available in amazingly small (2.50 x 2.50 mm, 0.4 mm pitch) WLCSP packages and BGA packages with 0.50 mm and 0.80 mm pitch
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Rapidly Compile Networks For Implementation On Lattice SensAI IP Cores
Neural Network Compiler
Analyze networks for fit in the chosen number of engines and allocated memory. After compilation, simulate networks for functionality and performance prior to testing in hardware. Graphical display of networks supports analysis and understanding.
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PLD For Bridging, Infinitely Reconfigurable I/O Expansion.
MachXO
*Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM*SRAM based logic can be reconfigured in milliseconds using JTAG port*IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS*Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting*Available in TQFP, csBGA, caBGA and ftBGA packages
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Enhance Secure Control Applications
MachXO3D
*Simplifies implementation of hardware security by integrating Root-of-Trust in your platform’s first on, last off device*Supports security throughout the product lifecycle including device manufacturing and transport, platform manufacturing, installation, operation and decommissioning
